MC9S12XD256CAG Datasheet, PDF (998/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
Table 24-15. PORTK Field Descriptions
Field
Description
7–0
PK[7,5:0]
Port K — Port K pins 7–0 can be used as general-purpose I/O. If the data direction bits of the associated I/O pins
are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read
except for bit 6 which reads “0”.
24.0.5.12 Port K Data Direction Register (DDRK)
7
6
5
4
3
2
1
0
R
0
DDRK7
DDRK5
DDRK4
DDRK3
DDRK2
DDRK1
DDRK0
W
Reset
0
0
0
0
0
0
0
0
Figure 24-14. Port K Data Direction Register (DDRK)
Read: Anytime.
Write: Anytime.
This register controls the data direction for port K. DDRK determines whether each pin (except PK6) is
an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0”
causes the associated pin to be a high-impedance input.
Table 24-16. DDRK Field Descriptions
Field
Description
7–0
Data Direction Port K
DDRK[7,5:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTK after changing the DDRK register.
24.0.5.13 Port T Data Register (PTT)
R
W
ECT
Reset
7
PTT7
IOC7
0
Read: Anytime.
Write: Anytime.
6
PTT6
5
PTT5
4
PTT4
3
PTT3
2
PTT2
IOC6
0
IOC5
IOC4
IOC3
IOC2
0
0
0
0
Figure 24-15. Port T Data Register (PTT)
1
PTT1
IOC1
0
0
PTT0
IOC0
0
1000
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor