MC9S12XD256CAG Datasheet, PDF (951/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

23.0.5.55 Port J Input Register (PTIJ)
7
6
5
4
3
2
1
0
R PTIJ7
PTIJ6
PTIJ5
PTIJ4
0
PTIJ2
PTIJ1
PTIJ0
W
Reset¹
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 23-57. Port J Input Register (PTIJ)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
associated pin values.
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This can be used to detect
overload or short circuit conditions on output pins.
23.0.5.56 Port J Data Direction Register (DDRJ)
7
6
5
4
3
2
1
0
R
0
DDRJ7
DDRJ6
DDRJ5
DDRJ4
DDRJ2
DDRJ1
DDRJ0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 23-58. Port J Data Direction Register (DDRJ)
Read: Anytime.
Write: Anytime.
This register configures each port J pin as either input or output.
The CAN forces the I/O state to be an output on PJ7 (TXCAN4) and an input on pin PJ6
(RXCAN4). The IIC takes control of the I/O if enabled. In these cases the data direction bits will
not change.
The SCI2 forces the I/O state to be an output for each port line associated with an enabled output
(TXD2). It also forces the I/O state to be an input for each port line associated with an enabled input
(RXD2). In these cases the data direction bits will not change.
The DDRJ bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.