MC9S12XD256CAG Datasheet, PDF (566/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Chapter 14 Voltage Regulator (S12VREG3V3V5)
The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency
is desired.
See Table 14-6 for the trimming effect of APITR.
NOTE
The first period after enabling the counter by APIFE might be reduced.
The API internal RC oscillator clock is not available if VREG_3V3 is in
Shutdown Mode.
14.4.8 Resets
This section describes how VREG_3V3 controls the reset of the MCU.The reset values of registers and
signals are provided in Section 14.3, “Memory Map and Register Definition”. Possible reset sources are
listed in Table 14-9.
Table 14-9. Reset Sources
Reset Source
Power-on reset
Low-voltage reset
Local Enable
Always active
Available only in Full Performance Mode
14.4.9 Description of Reset Operation
14.4.9.1 Power-On Reset (POR)
During chip power-up the digital core may not work if its supply voltage V_DD is below the POR
deassertion level (V_PORD). Therefore, signal POR, which forces the other blocks of the device into reset,
is kept high until V_DD exceeds V_PORD. The MCU will run the start-up sequence after POR deassertion.
The power-on reset is active in all operation modes of VREG_3V3.
14.4.9.2 Low-Voltage Reset (LVR)
For details on low-voltage reset, see Section 14.4.5, “Low-Voltage Reset (LVR)”.
14.4.10 Interrupts
This section describes all interrupts originated by VREG_3V3.
The interrupt vectors requested by VREG_3V3 are listed in Table 14-10. Vector addresses and interrupt
priorities are defined at MCU level.
Table 14-10. Interrupt Vectors
Interrupt Source
Low-voltage interrupt (LVI)
Local Enable
LVIE = 1; available only in Full Performance
Mode
MC9S12XDP512 Data Sheet, Rev. 2.21
566
Freescale Semiconductor