MC9S12XD256CAG Datasheet, PDF (559/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Chapter 14 Voltage Regulator (S12VREG3V3V5)
14.3.2 Register Descriptions
This section describes all the VREG_3V3 registers and their individual bits.
14.3.2.1 HT Control Register (VREGHTCL)
The VREGHTCL is reserved for test purposes. This register should not be written.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-2. HT Control Register (VREGHTCL)
14.3.2.2 Control Register (VREGCTRL)
The VREGCTRL register allows the configuration of the VREG_3V3 low-voltage detect features.
R
W
Reset
Field
2
LVDS
1
LVIE
0
LVIF
7
6
5
4
3
2
1
0
0
0
0
0
0
LVDS
LVIE
LVIF
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-3. Control Register (VREGCTRL)
Table 14-3. VREGCTRL Field Descriptions
Description
Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect.
0 Input voltage V_DDA is above level V_LVID or RPM or shutdown mode.
1 Input voltage V_DDA is below level V_LVIA and FPM.
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
Note: On entering the Reduced Power Mode the LVIF is not cleared by the VREG_3V3.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
559