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MC9S12XD256CAG Datasheet, PDF (329/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet | |||
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
TOF
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-18. Main Timer Interrupt Flag 2 (TFLG2)
Read: Anytime
Write used in the ï¬ag clearing mechanism. Writing a one to the ï¬ag clears the ï¬ag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the ï¬ag cannot be cleared via the normal ï¬ag clearing
mechanism (writing a one to the ï¬ag). Reference Section 7.3.2.6, âTimer
System Control Register 1 (TSCR1)â.
All bits reset to zero.
TFLG2 indicates when interrupt conditions have occurred. The ï¬ag can be cleared via the normal ï¬ag
clearing mechanism (writing a one to the ï¬ag) or via the fast ï¬ag clearing mechanism (Reference TFFCA
bit in Section 7.3.2.6, âTimer System Control Register 1 (TSCR1)â).
Table 7-17. TFLG2 Field Descriptions
Field
7
TOF
Description
Timer Overï¬ow Flag â Set when 16-bit free-running timer overï¬ows from 0xFFFF to 0x0000.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
329
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