MC9S12XD256CAG Datasheet, PDF (934/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
This register configures the drive strength of each port S output pin as either full or reduced. If the port is
used as input this bit is ignored.
Table 23-28. RDRS Field Descriptions
Field
Description
7–0
Reduced Drive Port S
RDRS[7:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
23.0.5.27 Port S Pull Device Enable Register (PERS)
7
R
PERS7
W
6
PERS6
5
PERS5
4
PERS4
3
PERS3
2
PERS2
1
PERS1
0
PERS0
Reset
1
1
1
1
1
1
1
1
Figure 23-29. Port S Pull Device Enable Register (PERS)
Read: Anytime.
Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or
as output in wired-OR (open drain) mode. This bit has no effect if the port is used as push-pull output. Out
of reset a pull-up device is enabled.
Table 23-29. PERS Field Descriptions
Field
Description
7–0
Pull Device Enable Port S
PERS[7:0] 0 Pull-up or pull-down device is disabled.
1 Either a pull-up or pull-down device is enabled.
23.0.5.28 Port S Polarity Select Register (PPSS)
R
W
Reset
7
PPSS7
0
6
PPSS6
5
PPSS5
4
PPSS4
3
PPSS3
2
PPSS2
0
0
0
0
0
Figure 23-30. Port S Polarity Select Register (PPSS)
1
PPSS1
0
Read: Anytime.
Write: Anytime.
This register selects whether a pull-down or a pull-up device is connected to the pin.
0
PPSS0
0
MC9S12XDP512 Data Sheet, Rev. 2.21
936
Freescale Semiconductor