MC9S12XD256CAG Datasheet, PDF (777/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Chapter 20 S12X Debug (S12XDBGV3) Module
20.4.5.3.1 Information Byte Organization
The format of the control information byte for both S12XCPU and XGATE modules is dependent upon
the active trace mode and tracing source as described below. In Normal, Loop1, or Pure PC modes tracing
of XGATE activity, XINF is used to store control information. In Normal, Loop1, or Pure PC modes
tracing of S12XCPU activity, CINF is used to store control information. In Detail Mode, CXINF contains
the control information
XGATE Information Byte
Bit 7
XSD
Bit 6
XSOT
Bit 5
XCOT
Bit 4
XDV
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Figure 20-24. XGATE Information Byte XINF
Field
7
XSD
6
XSOT
5
XCOT
4
XDV
Table 20-40. XINF Field Descriptions
Description
Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination
address. This is only used in Normal and Loop1 mode tracing.
0 Source Address
1 Destination Address or Start of Thread or Continuation of Thread
Source Of Thread Indicator — This bit indicates that the corresponding stored address is a start of thread
address. This is only used in Normal and Loop1 mode tracing.
NOTE. This bit only has effect on devices where the XGATE module supports multiple interrupt levels.
0 Stored address not from a start of thread
1 Stored address from a start of thread
Continuation Of Thread Indicator — This bit indicates that the corresponding stored address is the first
address following a return from a higher priority thread. This is only used in Normal and Loop1 mode tracing.
NOTE. This bit only has effect on devices where the XGATE module supports multiple interrupt levels.
0 Stored address not from a continuation of thread
1 Stored address from a continuation of thread
Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from
both sources in Normal, Loop1 and Pure PC modes, to indicate that the XGATE trace buffer entry is valid.
0 Trace buffer entry is invalid
1 Trace buffer entry is valid
X12X_CPU Information Byte
Bit 7
CSD
Bit 6
CVA
Bit 5
0
Bit 4
CDV
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Figure 20-25. S12XCPU Information Byte CINF
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
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