MC9S12XD256CAG Datasheet, PDF (745/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Chapter 20 S12X Debug (S12XDBGV3) Module
During BDM hardware accesses and whilst the BDM module is active, S12XCPU monitoring is disabled.
Thus breakpoints, comparators, and bus tracing mapped to the S12XCPU are disabled but XGATE bus
monitoring accessing the S12XDBG registers, including comparator registers, is still possible. While in
active BDM or during hardware BDM accesses, XGATE activity can still be compared, traced and can be
used to generate a breakpoint to the XGATE module. When the S12XCPU enters active BDM Mode
through a BACKGROUND command, with the S12XDBG module armed, the S12XDBG remains armed.
The S12XDBG module tracing is disabled if the MCU is secure. However, breakpoints can still be
generated if the MCU is secure.
Table 20-1. Mode Dependent Restriction Summary
BDM
Enable
x
0
0
1
1
BDM
Active
x
0
1
0
1
MCU
Secure
1
0
0
0
0
Comparator
Matches Enabled
Yes
Yes
Yes
XGATE only
Breakpoints
Possible
Tagging
Possible
Yes
Yes
Only SWI
Yes
Active BDM not possible when not enabled
Yes
Yes
XGATE only
XGATE only
Tracing
Possible
No
Yes
Yes
XGATE only
20.1.5 Block Diagram
TAGHITS
EXTERNAL TAGHI / TAGLO
XGATE S/W BREAKPOINT REQUEST
SECURE
S12XCPU BUS
XGATE BUS
COMPARATOR A
COMPARATOR B
COMPARATOR C
COMPARATOR D
MATCH0
MATCH1
MATCH2
MATCH3
TAGS
BREAKPOINT REQUESTS
S12XCPU & XGATE
TRIGGER
TAG &
TRIGGER
CONTROL
LOGIC
STATE
STATE
STATE SEQUENCER
TRACE
CONTROL
TRIGGER
READ TRACE DATA (DBG READ DATA BUS)
Figure 20-1. Debug Module Block Diagram
TRACE BUFFER
20.2 External Signal Description
The S12XDBG sub-module features two external tag input signals. See Device User Guide (DUG) for the
mapping of these signals to device pins. These tag pins may be used for the external tagging in emulation
modes only.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
747