MC9S12XD256CAG Datasheet, PDF (818/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2 Register Descriptions
Table 22-3 summarizes the effect on the various configuration bits, data direction (DDR), output level
(IO), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports.
The configuration bit PS is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
Table 22-3. Pin Configuration Summary
DDR
IO
RDR
PE
PS¹
IE²
Function
0
x
x
0
x
0
0
x
x
1
0
0
0
x
x
1
1
0
0
x
x
0
0
1
0
x
x
0
1
1
0
x
x
1
0
1
0
x
x
1
1
1
1
0
0
x
x
0
1
1
0
x
x
0
1
0
1
x
x
0
1
1
1
x
x
0
1
0
0
x
0
1
1
1
0
x
1
1
1
0
1
x
0
1
1
1
1
x
1
1
1 _{Always “0” on Port A, B, C, D, E, K, AD0, and AD1.}
2 _{Applicable only on Port P, H, and J.}
Input
Input
Input
Input
Input
Input
Input
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Pull Device
Disabled
Pull Up
Pull Down
Disabled
Disabled
Pull Up
Pull Down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Interrupt
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Disabled
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
NOTE
All register bits in this module are completely synchronous to internal
clocks during a register read.
MC9S12XDP512 Data Sheet, Rev. 2.21
820
Freescale Semiconductor