MC9S12XD256CAG Datasheet, PDF (685/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Chapter 18 Memory Mapping Control (S12XMMCV3)
Due to internal visibility of CPU accesses the CPU will be halted during XGATE or BDM access to any
PRR. This rule applies also in normal modes to ensure that operation of the device is the same as in
emulation modes.
A summary of PRR accesses:
• An aligned word access to a PRR will take 2 bus cycles.
• A misaligned word access to a PRRs will take 4 cycles. If one of the two bytes accessed by the
misaligned word access is not a PRR, the access will take only 3 cycles.
• A byte access to a PRR will take 2 cycles.
Table 18-23. PRR Listing
PRR Name
PORTA
PORTB
DDRA
DDRB
PORTC
PORTD
DDRC
DDRD
PORTE
DDRE
MMCCTL0
MODE
PUCR
RDRIV
EBICTL0
EBICTL1
Reserved
MMCCTL1
ECLKCTL
Reserved
PORTK
DDRK
PRR Local Address
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000C
0x000D
0x000E
0x000F
0x0012
0x0013
0x001C
0x001D
0x0032
0x0033
PRR Location
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
PIM
MMC
MMC
PIM
PIM
EBI
EBI
MMC
MMC
PIM
PIM
PIM
PIM
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
685