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MC9S12XD256CAG Datasheet, PDF (428/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet | |||
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Chapter 10 Freescaleâs Scalable Controller Area Network (S12MSCANV3)
Table 10-2. CANCTL1 Register Field Descriptions (continued)
Field
1
SLPAK
0
INITAK
Description
Sleep Mode Acknowledge â This ï¬ag indicates whether the MSCAN module has entered sleep mode (see
Section 10.4.5.4, âMSCAN Sleep Modeâ). It is used as a handshake ï¬ag for the SLPRQ sleep mode request.
Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will
clear the ï¬ag if it detects activity on the CAN bus while in sleep mode.
0 Running â The MSCAN operates normally
1 Sleep mode active â The MSCAN has entered sleep mode
Initialization Mode Acknowledge â This ï¬ag indicates whether the MSCAN module is in initialization mode
(see Section 10.4.5.5, âMSCAN Initialization Modeâ). It is used as a handshake ï¬ag for the INITRQ initialization
mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1,
CANBTR0, CANBTR1, CANIDAC, CANIDAR0âCANIDAR7, and CANIDMR0âCANIDMR7 can be written only by
the CPU when the MSCAN is in initialization mode.
0 Running â The MSCAN operates normally
1 Initialization mode active â The MSCAN has entered initialization mode
10.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0)
The CANBTR0 register conï¬gures various CAN bus timing parameters of the MSCAN module.
R
W
Reset:
7
SJW1
0
6
SJW0
5
BRP5
4
BRP4
3
BRP3
2
BRP2
0
0
0
0
0
Figure 10-6. MSCAN Bus Timing Register 0 (CANBTR0)
1
BRP1
0
0
BRP0
0
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 10-3. CANBTR0 Register Field Descriptions
Field
Description
7:6
SJW[1:0]
5:0
BRP[5:0]
Synchronization Jump Width â The synchronization jump width deï¬nes the maximum number of time quanta
(Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the
CAN bus (see Table 10-4).
Baud Rate Prescaler â These bits determine the time quanta (Tq) clock which is used to build up the bit timing
(see Table 10-5).
Table 10-4. Synchronization Jump Width
SJW1
0
0
1
1
SJW0
0
1
0
1
Synchronization Jump Width
1 Tq clock cycle
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
MC9S12XDP512 Data Sheet, Rev. 2.21
428
Freescale Semiconductor
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