MC9S12XD256CAG Datasheet, PDF (967/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
uncertain
t_pign
t_pval
Figure 23-77. Interrupt Glitch Filter on Port P, H, and J (PPS = 0)
Table 23-69. Pulse Detection Criteria
Pulse
STOP
Mode
Unit
STOP¹
Ignored
Uncertain
Valid
t_pulse ≤ 3
3 < t_pulse < 4
t_pulse ≥ 4
Bus clocks
Bus clocks
Bus clocks
t_pulse ≤ t_pign
t_pign < t_pulse < t_pval
t_pulse ≥ t_pval
1. These values include the spread of the oscillator frequency over
temperature, voltage and process.
t_pulse
Figure 23-78. Pulse Illustration
A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by
4 consecutive samples of an active level directly or indirectly.
The filters are continuously clocked by the bus clock in run and wait mode. In stop mode, the clock
is generated by an RC-oscillator in the port integration module. To maximize current saving the
RC oscillator runs only if the following condition is true on any pin individually:
Sample count <= 4 and interrupt enabled (PIE = 1) and interrupt flag not set (PIF = 0).
23.0.9 Expanded Bus Pin Functions
All peripheral ports T, S, M, P, H, J, AD0, and AD1 start up as general purpose inputs after reset.
Depending on the external mode pin condition, the external bus interface related ports A, B, C, D,
E, and K start up as general purpose inputs on reset or are configured for their alternate functions.