MC9S12XD256CAG Datasheet, PDF (929/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Table 23-20. DDRK Field Descriptions
Field
Description
7–0
DDRK[7:0]
Data Direction Port K
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTK after changing the DDRK register.
23.0.5.17 Port T Data Register (PTT)
R
W
ECT
Reset
7
PTT7
IOC7
0
Read: Anytime.
Write: Anytime.
6
PTT6
IOC6
0
5
PTT5
4
PTT4
3
PTT3
2
PTT2
IOC5
IOC4
IOC3
IOC2
0
0
0
0
Figure 23-19. Port T Data Register (PTT)
Table 23-21. PTT Field Descriptions
1
PTT1
IOC1
0
0
PTT0
IOC0
0
Field
7–0
PTT[7:0]
Description
Port T — Port T bits 7–0 are associated with ECT channels IOC7–IOC0 (refer to ECT section). When not used
with the ECT, these pins can be used as general purpose I/O.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port
register, otherwise the buffered pin input state is read.
23.0.5.18 Port T Input Register (PTIT)
7
R PTIT7
6
PTIT6
5
PTIT5
4
PTIT4
3
PTIT3
2
PTIT2
1
PTIT1
0
PTIT0
W
Reset¹
—
—
—
—
—
—
—
—
= Unimplemented or Reserved
Figure 23-20. Port T Input Register (PTIT)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
associated pin values.
Read: Anytime.
Write: Never, writes to this register have no effect.