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MC9S12XD256CAG Datasheet, PDF (1269/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet | |||
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Appendix A Electrical Characteristics
fC
<
----------2-----â
---ζ----â
---f--r--e----f---------
Ï
â
â
â
ζ
+
1 + ζ2â â
â
1--1-0--
â
fC < 4--f--r-â
--e-1--f-0- ;(ζ =
fC < 100kHz
0.9 )
And ï¬nally the frequency relationship is deï¬ned as
n = f--V--f-r--C-e---Of---- = 2 â
(synr + 1)
= 20
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
fC = 20 kHz:
R = 2-----â
---Ï---K--â
--Φ-n-----â
---f--C---= 2-----(â
--5-Ï--3---â
9---.2-1--0-H---â
--z-2--)-0---âk--â¦-H-----z- = 4.7kâ¦
The capacitance Cs can now be calculated as:
Cs = Ï-----2â
---f--â
C---ζ---2â
---R--- = f-0-C--.--5--â
-1--R-6--;(ζ = 0.9)
= 5.5nF = ~ 4.7nF
The capacitance Cp should be chosen in the range of:
C-2---0-s- ⤠Cp ⤠C-1---0-s-
CP = 470pF
A.5.3.2 Jitter Information
The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock fcmp, the
deviation from the reference clock fref is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4.
0
1
2
3
N-1
N
tmin1
tnom
tmax1
tminN
tmaxN
Figure A-4. Jitter Deï¬nitions
Freescale Semiconductor
MC9S12XDP512 Data Sheet, Rev. 2.21
1271
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