MC9S12XD256CAG Datasheet, PDF (601/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Chapter 16 Interrupt (S12XINTV1)
16.3.1.1 Interrupt Vector Base Register (IVBR)
Address: 0x0121
7
6
5
4
3
2
1
0
R
IVB_ADDR[7:0]
W
Reset
1
1
1
1
1
1
1
1
Figure 16-3. Interrupt Vector Base Register (IVBR)
Read: Anytime
Write: Anytime
Table 16-2. IVBR Field Descriptions
Field
Description
7–0
Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of
IVB_ADDR[7:0] reset these bits are set to 0xFF (i.e., vectors are located at 0xFF10–0xFFFE) to ensure compatibility to
HCS12.
Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine
the reset vector address. Therefore, changing the IVBR has no effect on the location of the three reset
vectors (0xFFFA–0xFFFE).
Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of
IVBR are ignored and the upper byte of the vector address is fixed as “0xFF”.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
601