MC9S12XD256CAG Datasheet, PDF (114/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Chapter 2 Clocks and Reset Generator (S12CRGV6)
Sampled RESET Pin
(64 cycles
after release)
1
1
1
0
Table 2-15. Reset Vector Selection
Clock Monitor
COP
Reset Pending Reset Pending
0
0
1
X
0
1
X
X
Vector Fetch
POR / LVR / Illegal Address Reset / External Reset
Clock Monitor Reset
COP Reset
POR / LVR / Illegal Address Reset / External Reset
with rise of RESET pin
NOTE
External circuitry connected to the RESET pin should not include a large
capacitance that would interfere with the ability of this signal to rise to a
valid logic 1 within 64 SYSCLK cycles after the low drive is released.
The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long
reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted
synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven
low for more than these 192 SYSCLK cycles (external reset), the internal reset remains asserted too.
RESET
SYSCLK
)(
)(
CRG drives RESET pin low
RESET pin
released
)
)
)
(
(
(
Possibly
SYSCLK
not
running
128 + n cycles
With n being
min 3 / max 6
cycles depending
on internal
synchronization
delay
64 cycles
Figure 2-25. RESET Timing
Possibly
RESET
driven low
externally
MC9S12XDP512 Data Sheet, Rev. 2.21
114
Freescale Semiconductor