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| MC9S12XD256CAG Datasheet, PDF (556/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet | |||
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Chapter 14 Voltage Regulator (S12VREG3V3V5)
14.1.3 Block Diagram
Figure 14-1 shows the function principle of VREG_3V3 by means of a block diagram. The regulator core
REG consists of two parallel subblocks, REG1 and REG2, providing two independent output voltages.
VDDR
VDDA
LVD
REG2
REG1
VBG
LVR
LVR
POR
VDDPLL
VSSPLL
VDD
POR
VSSA
VSS
VREGEN
Bus Clock
CTRL
API
Rate
Select
LVI
API
API
LVD: Low-Voltage Detect
LVR: Low-Voltage Reset
POR: Power-On Reset
REG: Regulator Core
CTRL: Regulator Control
API: Auto. Periodical Interrupt
PIN
Figure 14-1. VREG_3V3 Block Diagram
MC9S12XDP512 Data Sheet, Rev. 2.21
556
Freescale Semiconductor
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