MC9S12XD256CAG Datasheet, PDF (1022/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
Table 24-52. PIEJ Field Descriptions
Field
Description
7–0
PIEJ[7:6]
PIEJ[1:0]
Interrupt Enable Port J
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
24.0.5.57 Port J Interrupt Flag Register (PIFJ)
7
6
5
4
3
2
1
0
R
0
0
0
0
PIFJ7
PIFJ6
PIFJ1
PIFJ0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 24-59. Port J Interrupt Flag Register (PIFJ)
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSJ register. To clear this flag, write logic level “1” to the corresponding bit in the PIFJ
register. Writing a “0” has no effect.
Table 24-53. PIEJ Field Descriptions
Field
7–0
PIFJ[7:6]
PIFJ[1:0]
Description
Interrupt Flags Port J
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a logic level “1” clears the associated flag.
24.0.5.58 Port AD1 Data Register 0 (PT0AD1)
7
R
PT0AD115
W
Reset
0
6
5
4
3
2
PT0AD114 PT0AD113 PT0AD112 PT0AD111 PT0AD110
0
0
0
0
0
Figure 24-60. Port AD1 Data Register 0 (PT0AD1)
1
PT0AD19
0
0
PT0AD18
0
Read: Anytime.
Write: Anytime.
This register is associated with AD1 pins PAD[15:8]. These pins can also be used as general purpose I/O.
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MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor