MC9S12XD256CAG Datasheet, PDF (1180/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1)
START
Read: FCLKDIV register
Clock Register
Written
Check
FDIVLD
Set?
yes
no
Write: FCLKDIV register
NOTE: FCLKDIV needs to
be set once after each reset.
Read: FSTAT register
Address, Data,
Command
Buffer Empty Check
CBEIF
no
Set?
yes
Access Error and
Protection Violation
Check
1.
ACCERR/
yes
PVIOL
Set?
no
Write: Flash Block Address
and Dummy Data
Simultaneous
Multiple Flash Block
Decision
2.
Next
yes
Flash
Block?
no
Write: FCMD register
Mass Erase Command 0x41
3.
Write: FSTAT register
Clear CBEIF 0x80
Read: FSTAT register
Write: FSTAT register
Clear ACCERR/PVIOL 0x30
Decrement Global Address
by 128K (skip unimplemented Flash)
Bit Polling for
Command Completion
Check
CCIF
no
Set?
yes
EXIT
Figure 28-30. Example Mass Erase Command Flow
1182
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor