MC9S12XD256CAG Datasheet, PDF (617/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Chapter 17 Memory Mapping Control (S12XMMCV2)
Address
Register
Name
Bit 7
6
5
4
3
0x011C RAMWPC R
0
0
0
0
RPWE
W
0x011D RAMXGU R
1
W
XGU6
XGU5
XGU4
XGU3
0x011E RAMSHL R
1
W
SHL6
SHL5
SHL4
SHL3
0x011F RAMSHU R
1
W
SHU6
SHU5
SHU4
SHU3
= Unimplemented or Reserved
Figure 17-2. MMC Register Summary
2
0
XGU2
SHL2
SHU2
1
AVIE
XGU1
SHL1
SHU1
Bit 0
AVIF
XGU0
SHL0
SHU0
17.3.2 Register Descriptions
17.3.2.1 MMC Control Register (MMCCTL0)
Address: 0x000A PRR
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
1. ROMON is bit[0] of the register MMCTL1 (see Figure 1-10)
= Unimplemented or Reserved
3
CS3E
0
2
CS2E
0
Figure 17-3. MMC Control Register (MMCCTL0)
1
CS1E
0
0
CS0E
ROMON¹
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data is read from this register.
Write: Anytime. In emulation modes write operations will also be directed to the external bus.
Table 17-3. Chip Selects Function Activity
Register Bit
Chip Modes
NS
SS
NX
ES
CS3E, CS2E, CS1E, CS0E Disabled¹ Disabled Enabled² Disabled
1 _{Disabled: feature always inactive.}
2 _{Enabled: activity is controlled by the appropriate register bit value.}
EX
Enabled
ST
Enabled
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
617