MC9S12XD256CAG Datasheet, PDF (849/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.32 Port M Data Direction Register (DDRM)
R
W
Reset
7
DDRM7
0
6
DDRM6
5
DDRM5
4
DDRM4
3
DDRM3
2
DDRM2
0
0
0
0
0
Figure 22-34. Port M Data Direction Register (DDRM)
1
DDRM1
0
0
DDRM0
0
Read: Anytime.
Write: Anytime.
This register configures each port M pin as either input or output.
The CAN/SCI3 forces the I/O state to be an output for each port line associated with an enabled output
(TXCAN[3:0], TXD3). TheyAlso forces the I/O state to be an input for each port line associated with an
enabled input (RXCAN[3:0], RXD3). In those cases the data direction bits will not change.
The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is
disabled.
Table 22-33. DDRM Field Descriptions
Field
Description
7–0
DDRM[7:0]
Data Direction Port M
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTM or PTIM registers, when changing the DDRM register.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
851