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MC9S12XD256CAG Datasheet, PDF (1274/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet | |||
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Appendix A Electrical Characteristics
In Table A-26 the timing characteristics for master mode are listed.
Table A-26. SPI Master Mode Timing Characteristics
Num
1
1
2
3
4
5
6
9
10
11
12
13
C
Characteristic
D SCK frequency
D SCK period
D Enable lead time
D Enable lag time
D Clock (SCK) high or low time
D Data setup time (inputs)
D Data hold time (inputs)
D Data valid after SCK edge
D Data valid after SS fall (CPHA = 0)
D Data hold time (outputs)
D Rise and fall time inputs
D Rise and fall time outputs
Symbol
Min
Typ
fsck
1/2048
â
tsck
2
â
tlead
â
1/2
tlag
â
1/2
twsck
â
1/2
tsu
8
â
thi
8
â
tvsck
â
â
tvss
â
â
tho
0
â
trï¬
â
â
trfo
â
â
Max
1/2
2048
â
â
â
â
â
15
15
â
8
8
Unit
fbus
tbus
tsck
tsck
tsck
ns
ns
ns
ns
ns
ns
ns
fSCK/fbus
Figure A-8. Derating of maximum fSCK to fbus ratio in Master Mode
1/2
1/4
5
10 15 20 25 30 35 40
fbus [MHz]
In Master Mode the allowed maximum fSCK to fbus ratio (= minimum Baud Rate Divisor, pls. see
SPI Section) derates with increasing fbus.
A.7.2 Slave Mode
In Figure A-9 the timing diagram for slave mode with transmission format CPHA = 0 is depicted.
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MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
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