MC9S12XD256CAG Datasheet, PDF (85/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.3.2.1 CRG Synthesizer Register (SYNR)
The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop
divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency
by 2 x (SYNR + 1). PLLCLK will not be below the minimum VCO frequency (f_SCM).
PLLCLK = 2xOSCCLKx₍---⁽_{R--S---E-Y---F--N--D--R---V---+--+---1--1--}⁾--₎
NOTE
If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2
Bus Clock must not exceed the maximum operating system frequency.
7
R
0
W
6
5
4
0
SYN5
SYN4
Reset
0
0
0
0
= Unimplemented or Reserved
3
SYN3
0
2
SYN2
0
Figure 2-4. CRG Synthesizer Register (SYNR)
1
SYN1
0
Read: Anytime
Write: Anytime except if PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit and the track detector
bit.
0
SYN0
0
2.3.2.2 CRG Reference Divider Register (REFDV)
The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference
divider divides OSCCLK frequency by REFDV + 1.
7
R
0
W
6
5
4
3
2
1
0
REFDV5
REFDV4
REFDV3
REFDV2
REFDV1
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-5. CRG Reference Divider Register (REFDV)
Read: Anytime
Write: Anytime except when PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit and the track detector
bit.
0
REFDV0
0
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
85