MC9S12XD256CAG Datasheet, PDF (805/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet

Chapter 22
DP512 Port Integration Module (S12XDP512PIMV2)
22.1 Introduction
The S12XD family port integration module (below referred to as PIM) establishes the interface between
the peripheral modules including the non-multiplexed external bus interface module (S12X_EBI) and the
I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and
multiplexing on shared pins.
This document covers the description of:
• Port A, B used as address output of the S12X_EBI
• Port C, D used as data I/O of the S12X_EBI
• Port E associated with the S12X_EBI control signals and the IRQ, XIRQ interrupt inputs
• Port K associated with address output and control signals of the S12X_EBI
• Port T connected to the Enhanced Capture Timer (ECT) module
• Port S associated with 2 SCI and 1 SPI modules
• Port M associated with 4 MSCAN modules and 1 SCI module
• Port P connected to the PWM and 2 SPI modules — inputs can be used as an external interrupt
source
• Port H associated with 2 SCI modules — inputs can be used as an external interrupt source
• Port J associated with 1 MSCAN, 1 SCI, and 2 IIC modules — inputs can be used as an external
interrupt source
• Port AD0 and AD1 associated with one 8-channel and one 16-channel ATD module
Most I/O pins can be configured by register bits to select data direction and drive strength, to enable and
select pull-up or pull-down devices. Interrupts can be enabled on specific pins resulting in status flags.
The I/O’s of 2 MSCAN and all 3 SPI modules can be routed from their default location to alternative port
pins.
NOTE
The implementation of the PIM is device dependent. Therefore some
functions are not available on certain derivatives or 112-pin and 80-pin
package options.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
807