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MC9S12XD256CAG Datasheet, PDF (1268/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet | |||
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Appendix A Electrical Characteristics
A.5.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s voltage controlled oscillator (VCO) is
also the system clock source in self clock mode.
A.5.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good ï¬lter characteristics.
Cp
VDDPLL
Cs
R
Phase
XFC Pin
VCO
fosc
1
fref
refdv+1
D
KF
fvco
KV
Detector
fcmp
Loop Divider
1
1
synr+1
2
Figure A-3. Basic PLL Functional Diagram
The following procedure can be used to calculate the resistance and capacitance values using typical values
for K1, f1 and ich from Table A-23.
The grey boxes show the calculation for fVCO = 80 MHz and fref = 4 MHz. For example, these frequencies
are used for fOSC = 4-MHz and a 40-MHz bus clock.
The VCO gain at the desired VCO frequency is approximated by:
KV = K1 â
e(---f--K1----1-â----â
f--v-1--c-V---o----)
= â195MHz â V â
e1---2--â-6--1---â9---5-8---0- = -154.0MHz/V
The phase detector relationship is given by:
KΦ = â ich â
KV = â3.5µA â
(â154MHz â V) = 539.1Hz â â¦
ich is the current in tracking mode.
The loop bandwidth fC should be chosen to fulï¬ll the Gardnerâs stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
1270
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
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