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MC9S12XD256CAG Datasheet, PDF (58/1348 Pages) Freescale Semiconductor, Inc – MC9S12XDP512 Data Sheet | |||
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Chapter 1 Device Overview MC9S12XD-Family
The XCLKS signal selects the oscillator conï¬guration during reset low phase while a clock quality check
is ongoing. This is the case for:
⢠Power on reset or low-voltage reset
⢠Clock monitor reset
⢠Any reset while in self-clock mode or full stop mode
The selected oscillator conï¬guration is frozen with the rising edge of reset.
The pin can be conï¬gured to drive the internal system clock ECLKX2.
EXTAL
MCU
C1
Crystal or
Ceramic Resonator
XTAL
C2
VSSPLL
Figure 1-11. Loop Controlled Pierce Oscillator Connections (PE7 = 1)
EXTAL
MCU
XTAL
RB
RS
C1
Crystal or
Ceramic Resonator
C2
VSSPLL
Figure 1-12. Full Swing Pierce Oscillator Connections (PE7 = 0)
EXTAL
MCU
XTAL
CMOS-Compatible
External Oscillator
Not Connected
Figure 1-13. External Clock Connections (PE7 = 0)
1.2.3.17 PE6 / MODB / TAGHI â Port E I/O Pin 6
PE6 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is an input with a
MC9S12XDP512 Data Sheet, Rev. 2.21
58
Freescale Semiconductor
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