MC908MR16CFUE Datasheet, PDF (99/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

LVI Status and Control Register
9.4 LVI Status and Control Register
The LVI status register (LVISCR) flags V_DD voltages below the V_LVRX level.
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
TRPSEL
Write: R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 9-3. LVI Status and Control Register (LVISCR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the V_LVRX voltage for 32 to 40
CGMXCLK cycles. See Table 9-1. Reset clears the LVIOUT bit.
Table 9-1. LVIOUT Bit Indication
At Level:
V_DD > V_LVRX + V_LVHX
V_DD < V_LVRX
V_DD < V_LVRX
V_DD < V_LVRX
V_LVRX < V_DD < V_LVRX + V_LVHX
V_DD
For Number of CGMXCLK Cycles:
Any
< 32 CGMXCLK cycles
Between 32 & 40 CGMXCLK cycles
> 40 CGMXCLK cycles
Any
LVIOUT
0
0
0 or 1
1
Previous value
TRPSEL — LVI Trip Select Bit
This bit selects the LVI trip point. Reset clears this bit.
1 = 5 percent tolerance. The trip point and recovery point are determined by V_LVR1 and V_LVH1,
respectively.
0 = 10 percent tolerance. The trip point and recovery point are determined by V_LVR2 and V_LVH2,
respectively.
NOTE
If LVIRST and LVIPWR are 0s, note that when changing the tolerance, LVI
reset will be generated if the supply voltage is below the trip point.
9.5 LVI Interrupts
The LVI module does not generate interrupt requests.
9.6 Wait Mode
The WAIT instruction puts the MCU in low power-consumption standby mode.
With the LVIPWR bit in the configuration register programmed to 1, the LVI module is active after a WAIT
instruction.
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
99