MC908MR16CFUE Datasheet, PDF (38/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

Memory
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack
pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines. The CPU may overwrite data in
the RAM during a subroutine or during the interrupt stacking operation.
2.8 FLASH Memory (FLASH)
The FLASH memory is an array of 32,256 bytes with an additional 46 bytes of user vectors and one byte
of block protection.
NOTE
An erased bit reads as a 1 and a programmed bit reads as a 0.
Program and erase operations are facilitated through control bits in a memory mapped register. Details
for these operations appear later in this section.
Memory in the FLASH array is organized into two rows per page. The page size is 128 bytes per page.
The minimum erase page size is 128 bytes. Programming is performed on a row basis, 64 bytes at a time.
The address ranges for the user memory and vectors are:
• $8000–$FDFF, user memory
• $FF7E, block protect register (FLBPR)
• $FE08, FLASH control register (FLCR)
• $FFD2–$FFFF, reserved for user-defined interrupt and reset vectors
Programming tools are available from Freescale. Contact a local Freescale representative for more
information.
NOTE
A security feature prevents viewing of the FLASH contents.⁽¹⁾
2.8.1 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase operations.
Address: $FE08
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
HVEN MASS ERASE PGM
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 2-3. FLASH Control Register (FLCR)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for
unauthorized users.
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
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