MC908MR16CFUE Datasheet, PDF (132/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

Pulse-Width Modulator for Motor Control (PWMMC)
To allow for correction based on different current sensing methods or correction controlled by software,
the ISENS1 and ISENS0 bits in PWM control register 1 are provided to choose the correction method.
These bits provide correction according to Table 12-5.
Table 12-5. Correction Methods
Current Correction Bits
ISENS1 and ISENS0
00
01
10
11
Correction Method
Bits IPOL1, IPOL2, and IPOL3 used for correction
Current sensing on pins IS1, IS2, and IS3 occurs during the
dead-time.
Current sensing on pins IS1, IS2, and IS3 occurs at the half
cycle in center-aligned mode and at the end of the cycle in
edge-aligned mode.
If correction is to be done in software or is not necessary, setting ISENS1:ISENS0 = 00 or = 01 causes
the correction to be based on bits IPOL1, IPOL2, and IPOL3 in PWM control register 2. If correction is not
required, the user can initialize the IPOLx bits and then only load one PWM value register per PWM pair.
To allow the user to use a current sense scheme based upon sensed phase voltage during dead-time,
setting ISENS1:ISENS0 = 10 causes the polarity of the Ix pin to be latched when both the top and bottom
PWMs are off (for example, during the dead-time). At the 0 percent and 100 percent duty cycle
boundaries, there is no dead-time so no new current value is sensed.
To accommodate other current sensing schemes, setting ISENS1:ISENS0 = 11 causes the polarity of the
current sense pin to be latched half-way into the PWM cycle in center-aligned mode and at the end of the
cycle in edge-aligned mode. Therefore, even at 0 percent and 100 percent duty cycle, the current is
sensed.
Distortion correction is only available in complementary mode. At the beginning of the PWM period, the
PWM uses this latched current value or polarity bit to decide whether the top PWM value or bottom PWM
value is used. Figure 12-20 shows an example of top/bottom correction for PWMs 1 and 2.
NOTE
The IPOLx bits and the values latched on the ISx pins are buffered so that
only one PWM register is used per PWM cycle. If the IPOLx bits or the
current sense values change during a PWM period, this new value will not
be used until the next PWM period. The ISENSx bits are NOT buffered;
therefore, changing the current sensing method could affect the present
PWM cycle.
When the PWM is first enabled by setting PWMEN, PWM value registers 1, 3, and 5 will be used if the
ISENSx bits are configured for current sensing correction. This is because no current will have previously
been sensed.
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
132
Freescale Semiconductor