MC908MR16CFUE Datasheet, PDF (4/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

Revision History
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
August,
2001
October,
2001
December,
2001
November,
2003
July,
2005
Revision
Level
Description
Figure 2-1. MC68HC908MR32 Memory Map — Added FLASH Block Protect
Register (FLBPR) at address location $FF7E
3.0
Figure A-1. MC68HC908MR16 Memory Map — Added FLASH Block Protect
Register (FLBPR) at address location $FF7E
Page
Number(s)
29
306
4.0 3.3.3 Conversion Time — Reworked equations and text for clarity.
50
Figure 18-8. Monitor Mode Circuit — PTA7 and connecting circuitry added
279
Table 18-2. Monitor Mode Signal Requirements and Options — Switch locations
added to column headings for clarity
281
5.0
Section 16. Timer Interface A (TIMA) — Timer discrepancies corrected throughout
this section.
233
Section 17. Timer Interface B (TIMB) — Timer discrepancies corrected throughout
this section.
255
Reformatted to meet current publication standards
Throughout
2.8.2 FLASH Page Erase Operation — Procedure reworked for clarity
42
2.8.3 FLASH Mass Erase Operation — Procedure reworked for clarity
42
6.0
2.8.4 FLASH Program Operation — Procedure reworked for clarity
43
Figure 14-14. SIM Break Status Register (SBSR) — Clarified definition of SBSW bit.
207
19.5 DC Electrical Characteristics — Corrected maximum value for monitor mode
entry voltage (on IRQ)
291
19.6 FLASH Memory Characteristics — Updated table entries
292
6.1 Updated to meet Freescale identity guidelines.
Throughout
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
4
Freescale Semiconductor