MC908MR16CFUE Datasheet, PDF (135/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

Output Control
12.5.5 PWM Output Port Control
Conditions may arise in which the PWM pins need to be individually controlled. This is made possible by
the PWM output control register (PWMOUT) shown in Figure 12-22.
Address: $0025
Bit 7
Read: 0
Write:
6
OUTCTL
5
OUT6
4
OUT5
3
OUT4
2
OUT3
1
OUT2
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 12-22. PWM Output Control Register (PWMOUT)
Bit 0
OUT1
0
If the OUTCTL bit is set, the PWM pins can be controlled by the OUTx bits. These bits behave according
to Table 12-6.
Table 12-6. OUTx Bits
OUTx Bit
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
Complementary Mode
1 — PWM1 is active.
0 — PWM1 is inactive.
1 — PWM2 is complement of PWM 1.
0 — PWM2 is inactive.
1 — PWM3 is active.
0 — PWM3 is inactive.
1 — PWM4 is complement of PWM 3.
0 — PWM4 is inactive.
1 — PWM5 is active.
0 — PWM5 is inactive.
1 — PWM 6 is complement of PWM 5.
0 — PWM6 is inactive.
Independent Mode
1 — PWM1 is active.
0 — PWM1 is inactive.
1 — PWM2 is active.
0 — PWM2 is inactive.
1 — PWM3 is active.
0 — PWM3 is inactive.
1 — PWM4 is active.
0 — PWM4 is inactive.
1 — PWM5 is active.
0 — PWM5 is inactive.
1 — PWM6 is active.
0 — PWM6 is inactive.
When OUTCTL is set, the polarity options TOPPOL and BOTPOL will still affect the outputs. In addition,
if complementary operation is in use, the PWM pairs will not be allowed to be active simultaneously, and
dead-time will still not be violated. When OUTCTL is set and complementary operation is in use, the odd
OUTx bits are inputs to the dead-time generators as shown in Figure 12-15. Dead-time is inserted
whenever the odd OUTx bit toggles as shown in Figure 12-23. Although dead-time is not inserted when
the even OUTx bits change, there will be no dead-time violation as shown in Figure 12-24.
Setting the OUTCTL bit does not disable the PWM generator and current sensing circuitry. They continue
to run, but are no longer controlling the output pins. In addition, OUTCTL will control the PWM pins even
when PWMEN = 0. When OUTCTL is cleared, the outputs of the PWM generator become the inputs to
the dead-time and output circuitry at the beginning of the next PWM cycle.
NOTE
To avoid an unexpected dead-time occurrence, it is recommended that the
OUTx bits be cleared prior to entering and prior to exiting individual PWM
output control mode.
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
135