MC908MR16CFUE Datasheet, PDF (98/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

Low-Voltage Inhibit (LVI)
Once an LVI reset occurs, the MCU remains in reset until V_DD rises above a voltage, V_LVRX + V_LVHX.
V_DD must be above V_LVRX + V_LVHX for only one CPU cycle to bring the MCU out of reset. See
14.3.2.6 Low-Voltage Inhibit (LVI) Reset. The output of the comparator controls the state of the LVIOUT
flag in the LVI status register (LVISCR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
See 19.5 DC Electrical Characteristics.
Addr.
$FE0F
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
LVI Status and Control Register ^{Read: LVIOUT}
0
TRPSEL
0
0
0
0
0
(LVISCR) Write: R
R
R
R
R
R
R
See page 99.
Reset: 0
0
0
0
0
0
0
0
R = Reserved
Figure 9-2. LVI I/O Register Summary
9.3.1 Polled LVI Operation
In applications that can operate at V_DD levels below V_LVRX, software can monitor V_DD by polling the
LVIOUT bit. In the configuration register, the LVIPWR bit must be 1 to enable the LVI module, and the
LVIRST bit must be 0 to disable LVI resets. See Chapter 5 Configuration Register (CONFIG). TRPSEL
in the LVISCR selects V_LVRX.
9.3.2 Forced Reset Operation
In applications that require V_DD to remain above V_LVRX, enabling LVI resets allows the LVI module to
reset the MCU when V_DD falls to the V_LVRX level and remains at or below that level for nine or more
consecutive CPU cycles. In the CONFIG register, the LVIPWR and LVIRST bits must be 1s to enable the
LVI module and to enable LVI resets. TRPSEL in the LVISCR selects V_LVRX.
9.3.3 False Reset Protection
The V_DD pin level is digitally filtered to reduce false resets due to power supply noise. In order for the LVI
module to reset the MCU, V_DD must remain at or below V_LVRX for nine or more consecutive CPU cycles.
V_DD must be above V_LVRX + V_LVHX for only one CPU cycle to bring the MCU out of reset. TRPSEL in the
LVISCR selects V_LVRX + V_LVHX.
9.3.4 LVI Trip Selection
The TRPSEL bit allows the user to chose between 5 percent and 10 percent tolerance when monitoring
the supply voltage. The 10 percent option is enabled out of reset. Writing a 1 to TRPSEL will enable 5
percent option.
NOTE
The microcontroller is guaranteed to operate at a minimum supply voltage.
The trip point (VLVR1 or VLVR2) may be lower than this. See 19.5 DC
Electrical Characteristics.
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
98
Freescale Semiconductor