MC908MR16CFUE Datasheet, PDF (127/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

Output Control
When complementary operation is used, two additional features are provided:
• Dead-time insertion
• Separate top/bottom pulse width correction to correct for distortions caused by the motor drive
characteristics
If independent operation is chosen, each PWM has its own PWM value register.
12.5.2 Dead-Time Insertion
As shown in Figure 12-13, in complementary mode, each PWM pair can be used to drive
top-side/bottom-side transistors.
When controlling dc-to-ac inverters such as this, the top and bottom PWMs in one pair should never be
active at the same time. In Figure 12-13, if PWM1 and PWM2 were on at the same time, large currents
would flow through the two transistors as they discharge the bus capacitor. The IGBTs could be
weakened or destroyed.
Simply forcing the two PWMs to be inversions of each other is not always sufficient. Since a time delay is
associated with turning off the transistors in the motor drive, there must be a dead-time between the
deactivation of one PWM and the activation of the other.
A dead-time can be specified in the dead-time write-once register. This 8-bit value specifies the number
of CPU clock cycles to use for the dead-time. The dead-time is not affected by changes in the PWM period
caused by the prescaler.
Dead-time insertion is achieved by feeding the top PWM outputs of the PWM generator into dead-time
generators, as shown in Figure 12-14. Current sensing determines which PWM value of a PWM generator
pair to use for the top PWM in the next PWM cycle. See 12.5.3 Top/Bottom Correction with Motor Phase
Current Polarity Sensing. When output control is enabled, the odd OUT bits, rather than the PWM
generator outputs, are fed into the dead-time generators. See 12.5.5 PWM Output Port Control.
Whenever an input to a dead-time generator transitions, a dead-time is inserted (for example, both PWMs
in the pair are forced to their inactive state). The bottom PWM signal is generated from the top PWM and
the dead-time. In the case of output control enabled, the odd OUTx bits control the top PWMs, the even
OUTx bits control the bottom PWMs with respect to the odd OUTx bits (see Table 12-6). Figure 12-15
shows the effects of the dead-time insertion.
As seen in Figure 12-15, some pulse width distortion occurs when the dead-time is inserted. The active
pulse widths are reduced. For example, in Figure 12-15, when the PWM value register is equal to two,
the ideal waveform (with no dead-time) has pulse widths equal to four. However, the actual pulse widths
shrink to two after a dead-time of two was inserted. In this example, with the prescaler set to divide by
one and center-aligned operation selected, this distortion can be compensated for by adding or
subtracting half the dead-time value to or from the PWM register value. This correction is further described
in 12.5.3 Top/Bottom Correction with Motor Phase Current Polarity Sensing.
Further examples of dead-time insertion are shown in Figure 12-16 and Figure 12-17. Figure 12-16 shows
the effects of dead-time insertion at the duty cycle boundaries (near 0 percent and 100 percent duty
cycles). Figure 12-17 shows the effects of dead-time insertion on pulse widths smaller than the dead-time.
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
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