MC908MR16CFUE Datasheet, PDF (65/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

CGM Registers
4.4.6 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (f_XCLK) and comes
directly from the crystal oscillator circuit. Figure 4-3 shows only the logical relation of CGMXCLK to OSC1
and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
4.4.7 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks.
CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK,
divided by two.
4.4.8 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
4.5 CGM Registers
These registers control and monitor operation of the CGM:
• PLL control register (PCTL) — see 4.5.1 PLL Control Register
• PLL bandwidth control register (PBWC) — see 4.5.2 PLL Bandwidth Control Register
• PLL programming register (PPG) — see 4.5.3 PLL Programming Register
Figure 4-4 is a summary of the CGM registers.
Addr.
Register Name
Bit 7
6
5
4
3
$005C
Read:
PLLF
1
PLL Control Register
PLLIE
PLLON BCS
(PCTL) Write:
R
R
See page 66. _{Reset: 0}
0
1
0
1
$005D
PLL Bandwidth Control Register ^Read: _AUTO ^LOCK
ACQ
XLD
0
(PBWC) Write:
R
R
See page 67. _{Reset: 0}
0
0
0
0
$005E
PLL Programming Register ^Read:
(PPG) Write:
See page 68.
Reset:
MUL7
0
MUL6
1
MUL5
1
MUL4
0
VRS7
0
R = Reserved
Notes:
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 4-4. CGM I/O Register Summary
2
1
R
1
0
R
0
VRS6
1
1
1
R
1
0
R
0
VRS5
1
Bit 0
1
R
1
0
R
0
VRS4
0
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
65