MC908MR16CFUE Datasheet, PDF (104/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

Input/Output (I/O) Ports (PORTS)
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
DDRAx
PTAx
PTAx
READ PTA ($0000)
Figure 10-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a
logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 10-1 summarizes the operation of the port A pins.
Table 10-1. Port A Pin Functions
DDRA Bit
0
1
PTA Bit
X⁽¹⁾
X
I/O Pin Mode
Input, Hi-Z⁽²⁾
Output
Accesses to DDRA
Read/Write
DDRA[7:0]
DDRA[7:0]
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
Accesses to PTA
Read
Write
Pin
PTA[7:0]⁽³⁾
PTA[7:0]
PTA[7:0]
10.3 Port B
Port B is an 8-bit, general-purpose, bidirectional I/O port that shares its pins with the analog-to-digital
convertor (ADC) module.
10.3.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight port B pins.
Address:
Read:
Write:
Reset:
$0001
Bit 7
PTB7
6
PTB6
5
PTB5
4
3
PTB4
PTB3
Unaffected by reset
2
PTB2
1
PTB1
Bit 0
PTB0
Figure 10-5. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software-programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
104
Freescale Semiconductor