MC908MR16CFUE Datasheet, PDF (109/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

Port E
10.6.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a
logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the
output buffer.
Address:
Read:
Write:
Reset:
$000C
Bit 7
6
5
4
3
2
1
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1
0
0
0
0
0
0
0
Figure 10-14. Data Direction Register E (DDRE)
Bit 0
DDRE0
0
DDRE[7:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE[7:0], configuring all port E pins
as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 10-15 shows the port E I/O logic.
READ DDRE ($000C)
WRITE DDRE ($000C)
RESET
WRITE PTE ($0008)
DDREx
PTEx
PTEx
READ PTE ($0008)
Figure 10-15. Port E I/O Circuit
When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a
logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 10-5 summarizes the operation of the port E pins.
Table 10-5. Port E Pin Functions
DDRE Bit
0
1
PTE Bit
X⁽¹⁾
X
I/O Pin Mode
Input, Hi-Z⁽²⁾
Output
Accesses to DDRE
Read/Write
DDRE[7:0]
DDRE[7:0]
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
Accesses to PTE
Read
Write
Pin
PTE[7:0]⁽³⁾
PTE[7:0]
PTE[7:0]
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
109