MC908MR16CFUE Datasheet, PDF(213/282 Page) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

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MC908MR16CFUE Datasheet, PDF (213/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

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I/O Registers

OVRF â Overflow Bit

This clearable, read-only flag is set if software does not read the byte in the receive data register before

the next full byte enters the shift register. In an overflow condition, the byte already in the receive data

register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI

status and control register with OVRF set and then reading the receive data register. Reset clears the

OVRF bit.

1 = Overflow

0 = No overflow

MODF â Mode Fault Bit

This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission with

the MODFEN bit set. In a master SPI, the MODF flag is set if the SS pin goes low at any time with the

MODFEN bit set. Clear the MODF bit by reading the SPI status and control register (SPSCR) with

MODF set and then writing to the SPI control register (SPCR). Reset clears the MODF bit.

1 = SS pin at inappropriate logic level

0 = SS pin at appropriate logic level

SPTE â SPI Transmitter Empty Bit

This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift

register. SPTE generates an SPTE CPU interrupt request or an SPTE DMA service request if the

SPTIE bit in the SPI control register is set also.

NOTE

Do not write to the SPI data register unless the SPTE bit is high.

For an idle master of idle slave that has no data loaded into its transmit buffer, the SPTE will be set

again within two bus cycles since the transmit buffer empties into the shift register. This allows the user

to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot

occur until the transmission is completed. This implies that a back-to-back write to the transmit data

register is not possible. The SPTE indicates when the next write can occur.

Reset sets the SPTE bit.

1 = Transmit data register empty

0 = Transmit data register not empty

MODFEN â Mode Fault Enable Bit

This read/write bit, when set to 1, allows the MODF flag to be set. If the MODF flag is set, clearing the

MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low,

then the SS pin is available as a general-purpose I/O.

If the MODFEN bit is set, then this pin is not available as a general-purpose I/O. When the SPI is

enabled as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of

MODFEN. See 15.11.4 SS (Slave Select).

If the MODFEN bit is low, the level of the SS pin does not affect the operation of an enabled SPI

configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents

the MODF flag from being set. It does not affect any other part of SPI operation. See 15.6.2 Mode Fault

Error.

SPR1 and SPR0 â SPI Baud Rate Select Bits

In master mode, these read/write bits select one of four baud rates as shown in Table 15-4. SPR1 and

SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0.

MC68HC908MR32 â¢ MC68HC908MR16 Data Sheet, Rev. 6.1

Freescale Semiconductor

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