MC908MR16CFUE Datasheet, PDF (146/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

Pulse-Width Modulator for Motor Control (PWMMC)
12.9.4 PWM Control Register 1
PWM control register 1 (PCTL1) controls PWM enabling/disabling, the loading of new modulus, prescaler,
PWM values, and the PWM correction method. In addition, this register contains the software disable bits
to force the PWM outputs to their inactive states (according to the disable mapping register).
Address:
Read:
Write:
Reset:
$0020
Bit 7
6
5
4
3
2
1
DISX
DISY PWMINT PWMF ISENS1 ISENS0 LDOK
0
0
0
0
0
0
0
Figure 12-39. PWM Control Register 1 (PCTL1)
Bit 0
PWMEN
0
DISX — Software Disable Bit for Bank X Bit
This read/write bit allows the user to disable one or more PWM pins in bank X. The pins that are
disabled are determined by the disable mapping write-once register.
1 = Disable PWM pins in bank X.
0 = Re-enable PWM pins at beginning of next PWM cycle.
DISY — Software Disable Bit for Bank Y Bit
This read/write bit allows the user to disable one or more PWM pins in bank Y. The pins that are
disabled are determined by the disable mapping write-once register.
1 = Disable PWM pins in bank Y.
0 = Re-enable PWM pins at beginning of next PWM cycle.
PWMINT — PWM Interrupt Enable Bit
This read/write bit allows the user to enable and disable PWM CPU interrupts. If set, a CPU interrupt
will be pending when the PWMF flag is set.
1 = Enable PWM CPU interrupts.
0 = Disable PWM CPU interrupts.
NOTE
When PWMINT is cleared, pending CPU interrupts are inhibited.
PWMF — PWM Reload Flag
This read/write bit is set at the beginning of every reload cycle regardless of the state of the LDOK bit.
This bit is cleared by reading PWM control register 1 with the PWMF flag set, then writing a logic 0 to
PWMF. If another reload occurs before the clearing sequence is complete, then writing logic 0 to
PWMF has no effect.
1 = New reload cycle began.
0 = New reload cycle has not begun.
NOTE
When PWMF is cleared, pending PWM CPU interrupts are cleared (not
including fault interrupts).
ISENS1 and ISENS0 — Current Sense Correction Bits
These read/write bits select the top/bottom correction scheme as shown in Table 12-7.
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
146
Freescale Semiconductor