MC908MR16CFUE Datasheet, PDF(256/282 Page) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

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MC908MR16CFUE Datasheet, PDF (256/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

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Development Support

Features include:

â¢ Normal user-mode pin functionality

â¢ One pin dedicated to serial communication between monitor ROM and host computer

â¢ Standard mark/space non-return-to-zero (NRZ) communication with host computer

â¢ 4800 baudâ28.8 Kbaud communication with host computer

â¢ Execution of code in random-access memory (RAM) or ROM

â¢ FLASH programming

18.3.1 Functional Description

The monitor ROM receives and executes commands from a host computer. Figure 18-8 shows a sample

circuit used to enter monitor mode and communicate with a host computer via a standard RS-232

interface.

Simple monitor commands can access any memory address. In monitor mode, the MCU can execute

host-computer code in RAM while all MCU pins retain normal operating mode functions. All

communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and

multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR

configuration and requires a pullup resistor.

18.3.1.1 Entering Monitor Mode

There are two methods for entering monitor:

â¢ The first is the traditional M68HC08 method where VDD + VHI is applied to IRQ1 and the mode pins

are configured appropriately.

â¢ A second method, intended for in-circuit programming applications, will force entry into monitor

mode without requiring high voltage on the IRQ1 pin when the reset vector locations of the FLASH

are erased ($FF).

NOTE

For both methods, holding the PTC2 pin low when entering monitor mode

causes a bypass of a divide-by-two stage at the oscillator. The CGMOUT

frequency is equal to the CGMXCLK frequency, and the OSC1 input

directly generates internal bus clocks. In this case, the OSC1 signal must

have a 50 percent duty cycle at maximum bus frequency.

Table 18-1 is a summary of the differences between user mode and monitor mode.

Table 18-1. Mode Differences

Modes

User

Monitor

COP

Enabled

Disabled(1)

Rest

Vector High

$FFFE

$FEFE

Functions

Reset

Vector Low

$FFFF

$FEFF

Break

Vector High

$FFFC

$FEFC

Break

Vector Low

$FFFD

$FEFD

SWI

Vector High

$FFFC

$FEFC

SWI

Vector Low

$FFFD

$FEFD

1. If the high voltage (VDD + VHI) is removed from the IRQ1 pin or the RST pin, the SIM asserts its COP enable output. The

COP is a mask option enabled or disabled by the COPD bit in the configuration register.

18.3.1.2 Normal Monitor Mode

Table 18-2 shows the pin conditions for entering monitor mode.

MC68HC908MR32 â¢ MC68HC908MR16 Data Sheet, Rev. 6.1

256

Freescale Semiconductor

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