MC908MR16CFUE Datasheet, PDF(258/282 Page) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

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MC908MR16CFUE Datasheet, PDF (258/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

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Table 18-2. Monitor Mode Signal Requirements and Options

IRQ

RESET

(S1)

$FFFE

/$FFFF

PLL

PTC3

PTC4

PTC2

(S2)

External

Clock(1)

CGMOUT

Bus

Frequency

COP

For Serial

Communication(2)

PTA0

PTA7

(S3)

Baud

Rate(3) (4)

Comment

X GND

X

XX

X

X

X

0

0

Disabled X

X

0

No operation until reset goes high

VTST

VDD

or

VTST

1

0

9600 PTC3 and PTC2 voltages only required if

X

OFF 1

0

0

4.9152 4.9152

MHz

MHz

2.4576

MHz

Disabled

X

1

DNA

IRQ = VTST; PTC2 determines frequency

divider

VTST

VDD

or

VTST

VDD VDD

1

0

X

OFF 1

0

1

9.8304 4.9152

MHz

MHz

2.4576

MHz

Disabled

X

1

$FFFF

Blank

OFF X

X

X

9.8304 4.9152

MHz

MHz

2.4576

MHz

Disabled

1

X

0

1

9600

DNA

9600

DNA

PTC3 and PTC2 voltages only required if

IRQ = VTST; PTC2 determines frequency

divider

External frequency always divided by 4

VDD

or

VTST

$FFFF

Blank

OFF X

X

X

X

â

GND

â

Enabled X

X

â

Enters user mode â will encounter an

illegal address reset

VDD

or

GND

VDD

or

VTST

Non-$FF

Programmed

OFF

X

X

X

X

â

â

Enabled X

X

â Enters user mode

1. External clock is derived by a 32.768 kHz crystal or a 4.9152/9.8304 MHz off-chip oscillator.

2. DNA = does not apply, X = donât care

3. PAT0 = 1 if serial communication; PTA0 = X if parallel communication

4. PTA7 = 0 â serial, PTA7 = 1 â parallel communication for security code entry

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