MC908MR16CFUE Datasheet, PDF (28/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

Memory
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
Register Name
Bit 7
Port A Data Register
(PTA)
See page 103.
Read:
Write:
Reset:
PTA7
Port B Data Register
(PTB)
See page 104.
Read:
Write:
Reset:
PTB7
Port C Data Register ^{Read: 0}
(PTC) Write: R
See page 106. _Reset:
Port D Data Register ^{Read: 0}
(PTD) Write: R
See page 107. _Reset:
Data Direction Register A
(DDRA)
See page 103.
Read:
DDRA7
Write:
Reset: 0
Data Direction Register B
(DDRB)
See page 105.
Read:
DDRB7
Write:
Reset: 0
Data Direction Register C ^{Read: 0}
(DDRC) Write: R
See page 106. _{Reset: 0}
Unimplemented
6
PTA6
PTB6
PTC6
PTD6
R
DDRA6
0
DDRB6
0
DDRC6
0
5
PTA5
PTB5
PTC5
PTD5
R
DDRA5
0
DDRB5
0
DDRC5
0
4
3
PTA4
PTA3
Unaffected by reset
PTB4
PTB3
Unaffected by reset
PTC4
PTC3
Unaffected by reset
PTD4
PTD3
R
R
Unaffected by reset
DDRA4 DDRA3
0
0
DDRB4 DDRB3
0
0
DDRC4 DDRC3
0
0
2
PTA2
1
PTA1
Bit 0
PTA0
PTB2 PTB1 PTB0
PTC2 PTC1 PTC0
PTD2
R
PTD1
R
PTD0
R
DDRA2 DDRA1 DDRA0
0
0
0
DDRB2 DDRB1 DDRB0
0
0
0
DDRC2 DDRC1 DDRC0
0
0
0
$0008
$0009
$000A
Port E Data Register
(PTE)
See page 108.
Port F Data Register
(PTF)
See page 110.
Unimplemented
Read:
Write:
Reset:
Read:
Write:
Reset:
PTE7
0
R
PTE6
0
R
PTE5
PTF5
PTE4
PTE3
Unaffected by reset
PTF4
PTF3
Unaffected by reset
PTE2 PTE1 PTE0
PTF2 PTF1 PTF0
$000B
Unimplemented
$000C
$000D
U = Unaffected
Data Direction Register E
(DDRE)
See page 109.
Read:
DDRE7
Write:
Reset: 0
DDRE6
0
DDRE5
0
Data Direction Register F ^{Read: 0}
(DDRF) Write: R
See page 110. _Reset:
0
DDRF5
R
0
X = Indeterminate
R = Reserved
DDRE4 DDRE3
0
0
DDRF4 DDRF3
0
0
Bold = Buffered
DDRE2 DDRE1 DDRE0
0
0
0
DDRF2 DDRF1 DDRF0
0
0
0
= Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 1 of 8)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
28
Freescale Semiconductor