MC908MR16CFUE Datasheet, PDF (268/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

Electrical Specifications
19.6 FLASH Memory Characteristics
Characteristic
RAM data retention voltage
FLASH program bus clock frequency
FLASH read bus clock frequency
FLASH page erase time
<1 K cycles
>1 K cycles
FLASH mass erase time
FLASH PGM/ERASE to HVEN setup time
FLASH high-voltage hold time
FLASH high-voltage hold time (mass erase)
FLASH program hold time
FLASH program time
FLASH return to read time
FLASH cumulative program HV period
FLASH endurance⁽⁴⁾
FLASH data retention time⁽⁵⁾
Symbol
V_RDR
—
f_Read(1)
t_Erase
t_MErase
t_NVS
t_NVH
t_NVHL
t_PGS
t_PROG
t_RCV(2)
t_HV(3)
—
—
Min
1.3
1
0
0.9
3.6
4
10
5
100
5
30
1
—
10 k
15
Typ
—
—
—
1
4
—
—
—
—
—
—
—
—
100 k
100
Max
Unit
—
V
—
MHz
8M
Hz
1.1
ms
5.5
—
ms
—
µs
—
µs
—
µs
—
µs
40
µs
—
µs
4
ms
—
Cycles
—
Years
1. f_Read is defined as the frequency range for which the FLASH memory can be read.
2. t_RCV is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by
clearing HVEN to 0.
3. t_HV is defined as the cumulative high voltage programming time to the same row before next erase.
t_HV must satisfy this condition: t_NVS + t_NVH + t_PGS + (t_PROG x 32) ≤ t_HV maximum.
4. Typical endurance was evaluated for this product family. For additional information on how Freescale defines Typical
Endurance, please refer to Engineering Bulletin EB619.
5. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25°C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please
refer to Engineering Bulletin EB618.
19.7 Control Timing
Characteristic⁽¹⁾
Symbol
Min
Max
Unit
Frequency of operation⁽²⁾
Crystal option
External clock option⁽³⁾
f_OSC
1
dc⁽⁴⁾
8
MHz
32.8
Internal operating frequency
f_OP
—
8.2
MHz
RESET input pulse width low⁽⁵⁾
t_IRL
50
—
ns
1. V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc; timing shown with respect to 20% V_DD and 70% V_DD, unless otherwise noted
2. See 19.8 Serial Peripheral Interface Characteristics for more information.
3. No more than 10% duty cycle deviation from 50%.
4. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this
information.
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
268
Freescale Semiconductor