MC908MR16CFUE Datasheet, PDF(267/282 Page) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

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MC908MR16CFUE Datasheet, PDF (267/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

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19.5 DC Electrical Characteristics

DC Electrical Characteristics

Characteristic(1)

Output high voltage

(ILoad = â2.0 mA) all I/O pins

Output low voltage

(ILoad = 1.6 mA) all I/O pins

PWM pin output source current

(VOH = VDD â0.8 V)

PWM pin output sink current (VOL = 0.8 V)

Input high voltage, all ports, IRQs, RESET, OSC1

Input low voltage, all ports, IRQs, RESET, OSC1

VDD supply current

Run(3)

Wait(4)

Stop(5)

I/O ports high-impedance leakage current

Input current (input only pins)

Capacitance

Ports (as input or output)

Low-voltage inhibit reset(6)

Low-voltage reset/recover hysteresis

Low-voltage inhibit reset recovery

(VREC1 = VLVR1 + VLVH1)

Low-voltage inhibit reset

Low-voltage reset/recover hysteresis

Low-voltage inhibit reset recovery

(VREC2 = VLVR2 + VLVH2)

POR re-arm voltage(7)

POR rise time ramp rate(8)

POR reset voltage(9)

Monitor mode entry voltage (on IRQ)

Symbol

VOH

VOL

IOH

IOL

VIH

VIL

IDD

IIL

IIn

COut

CIn

VLVR1

VLVH1

VREC1

VLVR2

VLVH2

VREC2

VPOR

RPOR

VPORRST

VHi

Min

VDD â0.8

â

â7

20

0.7 x VDD

VSS

â

â

â

â

â

â

â

4.0

40

4.04

3.85

150

4.0

0

0.035

0

VDD + 2.5

Typ(2)

â

â

â

â

â

â

Max

â

0.4

â

â

VDD

0.3 x VDD

Unit

V

V

mA

mA

V

V

â

30

mA

â

12

mA

â

700

ÂµA

â

Â±10

ÂµA

â

Â±1

ÂµA

â

â

12

8

pF

4.35

4.65

V

90

150

mV

4.5

4.75

V

4.15

4.45

V

210

250

mV

4.4

4.6

V

â

100

mV

â

â

V/ms

700

800

V

â

8.0

V

1. VDD = 5.0 Vdc Â± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.

2. Typical values reflect average measurements at midpoint of voltage range, 25Â°C only.

3. Run (operating) IDD measured using external square wave clock source (fOSC = 8.2 MHz). All inputs 0.2 V from rail; no dc

loads; less than 100 pF on all outputs. CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly

affects run IDD; measured with all modules enabled

4. Wait IDD measured using external square wave clock source (fOSC = 8.2 MHz); all inputs 0.2 V from rail; no dc loads; less

than 100 pF on all outputs. CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait IDD;

measured with PLL and LVI enabled.

5. Stop IDD measured with PLL and LVI disengaged, OCS1 grounded, no port pins sourcing current. It is measured through

combination of VDD, VDDAD, and VDDA.

6. The low-voltage inhibit reset is software selectable. Refer to Chapter 9 Low-Voltage Inhibit (LVI).

7. Maximum is highest voltage that POR is guaranteed.

8. If minimum VDD is not reached before the internal POR is released, RST must be driven low externally until minimum VDD

is reached.

9. Maximum is highest voltage that POR is possible.

MC68HC908MR32 â¢ MC68HC908MR16 Data Sheet, Rev. 6.1

Freescale Semiconductor

267

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