MC908MR16CFUE Datasheet, PDF (92/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

External Interrupt (IRQ)
Interrupt signals on the IRQ pin are latched into the IRQ1 latch. An interrupt latch remains set until one of
the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears
the latch that caused the vector fetch.
• Software clear — Software can clear an interrupt latch by writing to the appropriate acknowledge
bit in the interrupt status and control register (ISCR). Writing a logic 1 to the ACK1 bit clears the
IRQ1 latch.
• Reset — A reset automatically clears both interrupt latches.
The external interrupt pins are falling-edge-triggered and are software-configurable to be both
falling-edge and low-level-triggered. The MODE1 bit in the ISCR controls the triggering sensitivity of the
IRQ pin.
When the interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software
clear, or reset occurs.
When the interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until
both of these occur:
• Vector fetch, software clear, or reset
• Return of the interrupt pin to logic 1
The vector fetch or software clear can occur before or after the interrupt pin returns to logic 1. As long as
the pin is low, the interrupt request remains pending.
When set, the IMASK1 bit in the ISCR masks all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. (See Figure 8-3.)
8.4 IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear,
or reset clears the IRQ latch.
If the MODE1 bit is set, the IRQ pin is both falling-edge-sensitive and low-level- sensitive. With MODE1
set, both of these actions must occur to clear the IRQ1 latch:
• Vector fetch, software clear, or reset — A vector fetch generates an interrupt acknowledge signal
to clear the latch. Software can generate the interrupt acknowledge signal by writing a logic 1 to
the ACK1 bit in the interrupt status and control register (ISCR). The ACK1 bit is useful in
applications that poll the IRQ pin and require software to clear the IRQ1 latch. Writing to the ACK1
bit can also prevent spurious interrupts due to noise. Setting ACK1 does not affect subsequent
transitions on the IRQ pin. A falling edge that occurs after writing to the ACK1 bit latches another
interrupt request. If the IRQ1 mask bit, IMASK1, is clear, the CPU loads the program counter with
the vector address at locations $FFFA and $FFFB.
• Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, the IRQ1 latch remains set.
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
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Freescale Semiconductor