MC908MR16CFUE Datasheet, PDF (101/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

Chapter 10
Input/Output (I/O) Ports (PORTS)
10.1 Introduction
Thirty-seven bidirectional input-output (I/O) pins and seven input pins form six parallel ports. All I/O pins
are programmable as inputs or outputs.
When using the 56-pin package version:
• Set the data direction register bits in DDRC such that bit 1 is written to a logic 1 (along with any
other output bits on port C).
• Set the data direction register bits in DDRE such that bits 0, 1, and 2 are written to a logic 1 (along
with any other output bits on port E).
• Set the data direction register bits in DDRF such that bits 0, 1, 2, and 3 are written to a logic 1 (along
with any other output bits on port F).
NOTE
Connect any unused I/O pins to an appropriate logic level, either V_DD or
V_SS. Although PWM6–PWM1 do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Addr.
$0000
$0001
$0002
$0003
$0004
Register Name
Port A Data Register
(PTA)
See page 103.
Port B Data Register
(PTB)
See page 104.
Port C Data Register
(PTC)
See page 106.
Port D Data Register
(PTD)
See page 107.
Data Direction Register A
(DDRA)
See page 103.
Read:
Write:
Bit 7
PTA7
6
PTA6
5
PTA5
4
PTA4
3
PTA3
2
PTA2
Reset:
Read:
Write:
PTB7
PTB6
PTB5
Unaffected by reset
PTB4 PTB3
PTB2
Reset:
Read: 0
Write: R
PTC6
PTC5
Unaffected by reset
PTC4 PTC3
PTC2
Reset:
Read: 0
Write: R
PTD6
R
PTD5
R
Unaffected by reset
PTD4 PTD3
R
R
PTD2
R
Reset:
Read:
Write:
DDRA7
DDRA6
DDRA5
Unaffected by reset
DDRA4 DDRA3
DDRA2
Reset: 0
R
0
0
= Reserved
0
0
0
= Unimplemented
Figure 10-1. I/O Port Register Summary
1
PTA1
PTB1
PTC1
PTD1
R
DDRA1
0
Bit 0
PTA0
PTB0
PTC0
PTD0
R
DDRA0
0
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
101