MC908MR16CFUE Datasheet, PDF (62/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

Clock Generator Module (CGM)
5. Calculate the bus frequency, f_BUS, and compare f_BUS with f_BUSDES.
f_BUS =
f_VCLK
4
Example: N = ^{32 MHz} = 8 MHz
4 MHz
6. If the calculated f_BUS is not within the tolerance limits of the application, select another f_BUSDES or
another f_RCLK.
7. Using the value 4.9152 MHz for f_NOM, calculate the VCO linear range multiplier, L. The linear range
multiplier controls the frequency range of the PLL.
L = round
(
f_VCLK
f_NOM
)
Example: L = ^{32 MHz} _{= 7 MHz}
4.9152 MHz
8. Calculate the VCO center-of-range frequency, f_VRS. The center-or-range frequency is the midpoint
between the minimum and maximum frequencies attainable by the PLL.
f_VRS = L x f_NOM
Example: f_VRS = 7 x 4.9152 MHz = 34.4 MHz
For proper operation,
f_VRS
–
f_VCLK
|
≤
f_NOM
2
CAUTION
Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU.
9. Program the PLL registers accordingly:
a. In the upper four bits of the PLL programming register (PPG), program the binary equivalent
of N.
b. In the lower four bits of the PLL programming register (PPG), program the binary equivalent
of L.
4.3.2.5 Special Programming Exceptions
The programming method described in 4.3.2.4 Programming the PLL does not account for possible
exceptions. A value of 0 for N or L is meaningless when used in the equations given. To account for these
exceptions:
• A 0 value for N is interpreted exactly the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the source for the base clock. See
4.3.3 Base Clock Selector Circuit.
4.3.3 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the
source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits
up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other.
During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
62
Freescale Semiconductor