MC908MR16CFUE Datasheet, PDF (35/282 Pages) Freescale Semiconductor, Inc – On-chip programming firmware for use with host personal computer, Clock generator module (CGM)

Addr.
$FE00
$FE01
$FE03
$FE08
$FE0C
$FE0D
$FE0E
$FE0F
$FF7E
Register Name
Bit 7
SIM Break Status Register ^Read: _R
(SBSR) Write:
See page 191. _Reset:
SIM Reset Status Register ^{Read: POR}
(SRSR) Write: R
See page 192. _{Reset: 1}
SIM Break Flag Control
Register (SBFCR)
See page 193.
Read:
Write:
Reset:
BCFE
0
FLASH Control Register Read: 0
(FLCR) _Write:
See page 38.
Reset: 0
Break Address Register High
(BRKH)
See page 254.
Read:
Write:
Reset:
Bit 15
0
Break Address Register Low ^Read: _{Bit 7}
(BRKL) Write:
See page 254. _{Reset: 0}
Break Status and Control
Register (BRKSCR)
See page 254.
Read:
Write:
Reset:
BRKE
0
LVI Status and Control Register
(LVISCR)
See page 99.
Read: LVIOUT
Write: R
Reset: 0
FLASH Block Protect Register
(FLBPR)
See page 43.
Read:
Write:
Reset:
BPR7
0
6
R
PIN
R
0
R
0
0
14
0
6
0
BRKA
0
0
R
0
BPR6
0
5
R
COP
R
0
R
0
0
13
0
5
0
0
0
TRPSEL
0
BPR5
0
4
R
ILOP
R
0
R
0
0
12
0
4
0
0
0
0
R
0
BPR4
0
Memory Map
3
2
1
Bit 0
R
R
BW
R
0
ILAD MENRST LVI
0
R
R
R
R
0
0
0
0
R
R
R
R
HVEN
0
11
0
3
0
0
MASS ERASE PGM
0
0
0
10
9
Bit 8
0
0
0
2
1
Bit 0
0
0
0
0
0
0
0
0
R
0
BPR3
0
0
0
R
0
BPR2
0
0
0
R
0
BPR1
0
0
0
R
0
BPR0
0
$FFFF
COP Control Register
(COPCTL)
See page 77.
Read:
Write:
Reset:
Low byte of reset vector
Clear COP counter
Unaffected by reset
U = Unaffected X = Indeterminate
R = Reserved
Bold = Buffered
= Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 8 of 8)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
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