MC68HC16Z1 Datasheet, PDF (98/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
Vector
Number
0
4
5
6
7
8
9–E
F
10
11
12
13
14
15
16
17
18
19 – 37
38 – FF
Table 4-5 Exception Vector Table
Vector
Address
0000
0002
0004
0006
0008
000A
000C
000E
0010
0012 – 001C
001E
0020
0022
0024
0026
0028
002A
002C
002E
0030
0032 – 006E
0070 – 01FE
Address
Space
P
P
P
P
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Type of
Exception
Reset — Initial ZK, SK, and PK
Reset — Initial PC
Reset — Initial SP
Reset — Initial IZ (Direct Page)
Breakpoint
Bus Error
Software Interrupt
Illegal Instruction
Division by Zero
Unassigned, Reserved
Uninitialized Interrupt
Unassigned, Reserved
Level 1 Interrupt Autovector
Level 2 Interrupt Autovector
Level 3 Interrupt Autovector
Level 4 Interrupt Autovector
Level 5 Interrupt Autovector
Level 6 Interrupt Autovector
Level 7 Interrupt Autovector
Spurious Interrupt
Unassigned, Reserved
User-Defined Interrupts
4.13.2 Exception Stack Frame
During exception processing, the contents of the program counter and condition code
register are stacked at a location pointed to by SK : SP. Unless it is altered during ex-
ception processing, the stacked PK : PC value is the address of the next instruction in
the current instruction stream, plus $0006. Figure 4-6 shows the exception stack
frame.
Low Address
High Address
Condition Code Register
Program Counter
⇐ SP After Exception Stacking
⇐ SP Before Exception Stacking
Figure 4-6 Exception Stack Frame Format
4-38
CENTRAL PROCESSING UNIT
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M68HC16 Z SERIES
USER’S MANUAL