MC68HC16Z1 Datasheet, PDF (380/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
D.2.1 SIM Module Configuration Register
SIMCR — SIM Module Configuration Register
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15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EXOFF FRZSW FRZBM 0 _RSVD¹ 0
SHEN[1:0] SUPV MM
0
0
IARB[3:0]
RESET:
0
1
1
0 DATA11 0
0
0
1
1
0
0
1
1
1
1
NOTES:
1. This bit must be left at zero. Pulling DATA11 high during reset ensures this bit remains zero. A one in this bit could
allow the MCU to enter an unsupported operating mode.
SIMCR controls system configuration. SIMCR can be read or written at any time, ex-
cept for the module mapping (MM) bit, which can only be written once after reset, and
the reserved bit, which is read-only. Write has no effect.
EXOFF — External Clock Off
0 = The CLKOUT pin is driven during normal operation.
1 = The CLKOUT pin is placed in a high-impedance state.
FRZSW — Freeze Software Enable
0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer
continue to operate, allowing interrupts during background debug mode.
1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer
are disabled, preventing interrupts during background debug mode.
FRZBM — Freeze Bus Monitor Enable
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
SHEN[1:0] — Show Cycle Enable
The SHEN field determines how the external bus is driven during internal transfer op-
erations. A show cycle allows internal transfers to be monitored externally.
Table D-3 indicates whether show cycle data is driven externally, and whether exter-
nal bus arbitration can occur. To prevent bus conflict, external devices must not be se-
lected during show cycles.
Table D-3 Show Cycle Enable Bits
SHEN[1:0]
00
01
10
11
Action
Show cycles disabled, external arbitration enabled
Show cycles enabled, external arbitration disabled
Show cycles enabled, external arbitration enabled
Show cycles enabled, external arbitration enabled;
internal activity is halted by a bus grant
SUPV — Supervisor/User Data Space
This bit has no effect because the CPU16 always operates in the supervisor mode.
REGISTER SUMMARY
M68HC16 Z SERIES
D-6
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