MC68HC16Z1 Datasheet, PDF (329/500 Pages) Freescale Semiconductor, Inc – M68HC16Z Series

Freescale Semiconductor, Inc.
Table A-27 Low Voltage QSPI Timing
(V_DD and V_DDSYN = 2.7 to 3.6 Vdc, V_SS = 0 Vdc, T_A = T_L to T_H)¹
Num
Function
Operating Frequency
1 Master
Slave
Cycle Time
2 Master
Slave
Enable Lead Time
3 Master
Slave
Symbol
Min
f_op
DC
DC
t_qcyc
4
4
t_lead
2
2
Max
1/4
1/4
510
—
128
—
Enable Lag Time
4 Master
Slave
Clock (SCK) High or Low Time
5 Master
Slave²
Sequential Transfer Delay
6 Master
Slave (Does Not Require Deselect)
Data Setup Time (Inputs)
7 Master
Slave
t_lag
—
1/2
2
—
t_sw
2 t_cyc – 60 255 t_cyc
2 t_cyc – n
—
t_td
17
8192
13
—
t_su
20
—
20
—
Data Hold Time (Inputs)
8 Master
Slave
9 Slave Access Time
10 Slave MISO Disable Time
Data Valid (after SCK Edge)
11 Master
Slave
t_hi
30
—
20
—
t_a
—
1
t_dis
—
2
t_v
—
50
—
50
Data Hold Time (Outputs)
12 Master
Slave
Rise Time
13 Input
Output
Fall Time
14 Input
Output
NOTES:
1. Refer to notes in Table A-28.
t_ho
0
—
0
—
t_ri
—
2
t_ro
—
30
t_fi
—
2
t_fo
—
30
Unit
f_sys
f_sys
t_cyc
t_cyc
t_cyc
t_cyc
SCK
t_cyc
ns
ns
t_cyc
t_cyc
ns
ns
ns
ns
t_cyc
t_cyc
ns
ns
ns
ns
µs
ns
µs
ns
M68HC16 Z SERIES
USER’S MANUAL
ELECTRICAL CHARACTERISTICS
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Go to: www.freescale.com
A-45